PhD Project: Neuromorphic Silicon for Non-invasive Communication BCIs

PhD Project: Neuromorphic Silicon for Non-invasive Communication BCIs

Decision overview

Promising, with substantial technical risk and competitive funding. The saved Southampton project evidence gives Dr Majid Zamani as lead supervisor and lists a Monday, 30 November 2026 deadline. Current application availability and the closing time/timezone have not been verified. The project designs a neuromorphic processor for scalp-EEG communication BCIs, moving from event encoding and spiking decoders to RTL/FPGA and possibly silicon tape-out, then live-human EEG validation in a fully on-device closed-loop task. official Southampton project page.

University and programme signal

The project description places the research in Electronics and Computer Science (ECS), with relevance to digital health, biomedical engineering and neuromorphic hardware. The application route names the Faculty of Engineering and Physical Sciences (FEPS) and PhD Electronic & Electrical Engineering (7092); the saved record also maps the department field to FEPS. The material does not explain the administrative relationship between the research home and degree-awarding department, so applicants should confirm it. The Centre for Neuromorphic Technologies provides context for energy-efficient brain-inspired hardware and algorithms, but does not establish a project tape-out budget. ECS PGR page, Centre for Neuromorphic Technologies.

Supervisor and lab assessment

Zamani’s profile is a strong fit for hardware-efficient BCI processing. It lists implantable BMI, hardware-efficient processing frameworks and applied AI in biomedical engineering, and describes work on scalability, signal processing, sensing, energy efficiency and miniaturisation. That supports the proposed extension from implantable neural processing to non-invasive EEG head-worn computation. Majid Zamani profile.

The key caveat is hardware maturity. The project says RTL and FPGA are expected, while a fabricated device is conditional “if the project supports it.” Applicants should not treat tape-out as guaranteed. The real thesis may succeed through a well-benchmarked RTL/FPGA processor and live EEG demonstration even without silicon fabrication. Southampton cleanroom/Zepler evidence supports a local hardware ecosystem, but project-specific budget and fabrication route must be confirmed. official project page, Zepler cleanroom lithography.

Recent publications and research quality

Implantable processing evidence: 2026 review and 2023 studies

Zamani’s 2026 Journal of Neural Engineering review is highly relevant because it frames the bandwidth-power-latency bottleneck in invasive BCIs and argues for low-power on-implant processing. His 2023 IEEE Access work on hardware-efficient spike sorting and neural signal processing supports the engineering base for real-time neural computation, even though the present project is non-invasive EEG rather than implanted spikes. JNE 2026 review, IEEE Access 2023 hardware-efficient spike sorting, IEEE Access 2023 DNN spike sorting.

Non-invasive decoding foundations

The project-listed research foundations are also important. The 2026 Nature Neuroscience Brain2Qwerty paper shows non-invasive sentence decoding from MEG/EEG, but also makes clear that non-invasive decoding still lags invasive performance and is not yet a real-time clinical product. The 2023 Nature Machine Intelligence paper on speech perception from non-invasive recordings supports the idea that non-invasive neural decoding is improving, while remaining dependent on datasets, models and recording modality. Brain2Qwerty Nature Neuroscience 2026, Nature Machine Intelligence 2023.

The publication summaries distinguish a review from original engineering and decoding studies. They do not establish that implanted-signal performance transfers to scalp EEG, or that the present project has reproduced those results. No complete methods audit or independent replication is established by the available dossier.

Research direction, ethics and individual risk

Current non-invasive BCI decoding relies on laptops or cloud computing, which limits device size, portability and responsiveness. Moving computation onto a head-worn device requires accuracy, latency and power to be managed together; this is the hardware gap the project addresses. It adapts and extends the group’s neuromorphic AI architecture for implantable neural processing to scalp EEG.

The work starts by encoding continuous scalp EEG as sparse events while preserving phase, amplitude and spectral information needed for decoding; this differs from vision-inspired encodings that typically discard those features. It then develops and quantises event-driven decoders and benchmarks them against deep-learning baselines on motor imagery, evoked or steady-state responses, and mental-state classification. To address poor cross-session and cross-subject generalisation, the architecture adds lightweight on-chip learning for local recalibration without full retraining.

The design is co-developed with the analogue front end to degrade gracefully under muscle activity, eye movement, motion and mains interference. The implementation proceeds through Register-Transfer Level (RTL) design and FPGA prototyping, with joint characterisation of accuracy, latency and power. Silicon tape-out is conditional on feasibility. Expected outputs include event encoding for EEG-based BCI applications, benchmarked spiking decoders, a processor architecture with RTL and FPGA prototype, and a real-time, fully on-device closed-loop demonstration using live human EEG.

Ethical and individual-risk boundaries must stay explicit. The planned validation uses live human EEG in a closed-loop task, but this does not imply a clinical communication product, patient benefit or medical approval. Non-invasive BCIs also raise privacy and consent concerns because brain data can reveal sensitive cognitive or health information. The student should ask how human-participant ethics, data governance, mental-state inference limits and participant burden will be handled.

Funding, living cost and application route

Funding is competition-based. Southampton’s funding page says competition-funded projects go ahead if funding is awarded. The official project page lists funding routes for UK and international students, including Horizon Europe fee waivers, Presidential Bursaries and school studentships, but these are competitive or conditional routes. It does not state a guaranteed stipend amount, duration or overseas-fee coverage for an individual applicant. official project page, Southampton PhD funding, Presidential bursaries.

The listed deadline is Monday, 30 November 2026; current availability and the closing time/timezone are unconfirmed. The saved application route is Research, 2026/27, FEPS, full-time or part-time, PhD Electronic & Electrical Engineering (7092), with Zamani named in section 2. Required materials are a research proposal, CV, two academic references, transcripts and degree certificates to date, and English evidence if applicable. Confirm the applicable intake and code with the University. official project page, Southampton accommodation costs.

The Horizon Europe waiver is residence-based, not a Chinese-nationality ban: residence in a listed country is required, China is not on the list cited in the saved material, and the automatic waiver covers the overseas-to-UK fee difference for 3.5 years without providing a stipend. A Chinese citizen resident in a listed country should request individual eligibility assessment. Official Horizon Europe fee waiver.

Chinese/international eligibility and fit

Chinese applicants may use the international-equivalence route, but individual qualifications and funding still require confirmation. The minimum is a UK 2:1 equivalent in electronic engineering, computer science, biomedical engineering, physics or a related subject. Essential skills are strong programming and a solid grounding in signal processing and machine learning. The advert says “Python and C/C++ or MATLAB”; confirm the intended language combination. Numerical English requirements and exemptions are not stated. Southampton China equivalencies, Southampton English requirements.

Best-fit applicants will show EEG/BCI signal processing, embedded ML, neuromorphic computing, RTL/FPGA, quantisation, low-power hardware, DSP and experimental human-subject data handling. A pure software ML profile is weaker unless it includes hardware or real-time constraints.

Career and risk assessment

The training could support work in neuromorphic hardware, low-power AI accelerators, BCI systems, edge biomedical devices and semiconductor R&D; those are skill-based directions rather than verified graduate outcomes. UK semiconductor and wireless strategy evidence supports the broader field. The main risk is technical integration: one PhD may be stretched across EEG encoding, decoders, on-chip learning, analogue-front-end co-design, RTL/FPGA, possible silicon and human validation. UK National Semiconductor Strategy, UK Wireless Infrastructure Strategy.

Equality and Applicant Support

The announcement welcomes applicants regardless of gender, ethnicity, disability, sexual orientation or age, and says it will give full consideration to people seeking flexible working patterns and those who have taken a career break. It also mentions the University’s maternity policy, onsite childcare and wellbeing/work-life benefits, without specifying how these apply to doctoral applicants. The saved announcement does not describe a disability-declaration support procedure or an additional personal-statement arrangement. official Southampton project page.

Verification questions

1. Confirm the exact funding route, stipend amount, duration, overseas-fee coverage and ranking process.
2. Confirm whether 30 November 2026 has a time/time zone, and whether rolling funding makes early submission essential.
3. Ask whether the 2026/27 application route is correct and what start date is expected.
4. Confirm whether tape-out is budgeted or only a stretch goal; ask for FPGA/RTL success metrics if no fabrication occurs.
5. Ask what EEG equipment, datasets, human-participant ethics approval and data-governance plan are in place.
6. Ask whether ATAS, export-control or semiconductor/BCI-sensitive technology restrictions apply to Chinese applicants.
7. Confirm the two FEPS email addresses and their roles; the saved advert concatenates them as doctoralcollege-admissions@soton.ac.ukfeps-pgr-apply@soton.ac.uk.

Evidence and Sources

Project, Training And Resources

• official Southampton project page
• ECS postgraduate research
• Centre for Neuromorphic Technologies
• Majid Zamani profile
• Zepler cleanroom lithography

Funding And Eligibility

• Southampton PhD funding
• Presidential Bursaries
• Horizon Europe fee waiver
• accommodation fees
• China qualification equivalencies
• English-language requirements

Research And Field Context

• JNE 2026 review
• IEEE Access 2023 hardware-efficient spike sorting
• IEEE Access 2023 DNN spike sorting
• Brain2Qwerty
• Nature Machine Intelligence 2023 speech-perception decoding
• UK National Semiconductor Strategy
• UK Wireless Infrastructure Strategy